Many efforts have been made in research and development of various flat display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD), and some species of the flat display devices are already applied to displays of various equipment types.
Amongst the various flat display devices, the liquid crystal display (LCD) device has been widely used due to advantageous characteristics of thin profile, light weight, and low power consumption, when the LCD device is substituted for a Cathode Ray Tube (CRT). In addition to the mobile-type LCD devices such as a display for a notebook computer, LCD devices have been developed for computer monitors and for television, to display broadcasting signals.
Despite various technical developments in the LCD technology with applications in different fields, research in enhancing the picture quality of the LCD device has been in some respects lacking as compared to other features and advantages of the LCD device. In order to use the LCD device in various fields as a general display, it is desirable for the LCD device to have a high quality picture, such as high resolution and high luminance with a large-sized screen while still maintaining the light weight, thin profile, and low power consumption characteristics.
An LCD device includes an LCD panel for displaying a picture image, and a driver for applying a driving signal to the LCD panel. Also, the LCD panel includes first and second substrates bonded to each other at predetermined intervals, and a liquid crystal layer between the first and second substrates. The first substrate (TFT array substrate) is comprised of a plurality of gate lines arranged in one direction at fixed intervals, a plurality of data lines arranged at fixed intervals perpendicular to the plurality of gate lines, a plurality of pixel electrodes arranged in a matrix in the pixel regions defined by the plurality of gate and data lines crossing each other, and a plurality of thin film transistors being switched according to signals of the gate lines for transmitting signals of the data lines to the respective pixel electrodes.
A related art LCD device will be described with reference to the accompanying drawings. An equivalent circuit diagram of one pixel in a related art LCD device is shown in FIG. 1. The circuit includes a thin film transistor T, a liquid crystal capacitance CLC, and a storage capacitor Cst. The thin-film transistor T has a source electrode and a gate electrode connected with a data line D and a gate line G, respectively, formed on a first substrate. A liquid crystal capacitance CLC is formed between a pixel electrode and a common electrode C, the pixel electrode connected with a drain electrode of the thin-film transistor T, and the common electrode C formed on an upper substrate. The storage capacitor Cst is formed between the pixel electrode connected with the drain electrode of the thin-film transistor T and the adjacent gate line or an additional storage line.
When a gate signal is applied to the gate line G, the thin-film transistor T is turned on, so that a gray level voltage, set according to a data signal from the data line D, is applied to each frame of the pixel. An electric field, corresponding to a difference between the gray level voltage applied to the pixel and a common voltage applied to the common electrode C, is applied to a liquid crystal layer, thereby controlling light transmittance on the basis of intensity of the electric field. The storage capacitor Cst maintains the gray level voltage applied to the pixel during one picture frame time interval, thereby displaying an image for one frame interval, as defined by the data.
If an electric field of a fixed direction is continuously applied to the liquid crystal layer, the liquid crystal layer deteriorates. To prevent such deterioration of the liquid crystal layer, the gray level voltage applied from the data line D is provided alternately with a positive (+) polarity or a negative (−) polarity with respect to the common voltage of the common electrode C. That is, when applying the gray level voltage to one pixel, a gray level voltage of positive polarity with respect to the common voltage is applied to the first frame, and a gray level voltage of negative polarity with respect to the common voltage is applied to the second frame, such that gray level voltages of the positive polarity and the negative polarity are applied to each pixel during alternate frame intervals. This driving method is referred to as an inversion driving method.
An effective value of the voltage applied to the liquid crystal layer is determined as the voltage corresponding to the difference between the gray level voltage applied to the pixel electrode and the common voltage applied to the common electrode C. When driving the LCD device by the inversion driving method, the common voltage should be maintained at a constant level so that the gray level voltage of positive polarity and the gray level voltage of negative polarity are symmetric with respect to the common voltage, and the gray level voltages of positive and negative polarity applied to the pixel have the same absolute value.
As shown in FIG. 1, a parasitic capacitance Ccd is generated at a crossing portion of the common electrode C transmitting the common voltage and the data line D transmitting the gray level voltage, thereby generating a coupling phenomenon. As a result, the common voltage is distorted due to the gray level voltage.
FIG. 2 is a waveform diagram of the undistorted common voltage. FIG. 3 is a waveform diagram showing distortion of the common voltage by the gray level voltage of positive polarity and the gray level voltage of negative polarity.
As shown in FIG. 2, the common voltage is a voltage having a constant D.C. level. By the coupling phenomenon, as shown in FIG. 3, the common voltage is distorted to a signal having an A.C. level having rising ripple and falling ripple corresponding to the gray level voltage of positive polarity and negative polarity. A parasitic capacitance Cgd is present at the crossing portion of the data line D and the gate line G, thereby generating the coupling phenomenon. As a result, the gate signal transmitted from the gate line G is synchronized with the distortion of the common voltage, whereby the gate signal is distorted by the rising ripple and falling ripple according to the gray level voltage of positive polarity and the gray level voltage of negative polarity. To prevent the distortion of common voltage, a method for compensating the distortion of common voltage by using the distorted common voltage and an inverted common voltage having a phase of 180° has been studied and researched.
A related art common voltage generation circuit will be described with reference to the accompanying drawings. FIG. 4 is a schematic view of a related art common voltage generation circuit. FIG. 5 is a waveform diagram of a compensated common voltage.
As shown in FIG. 4, the related art common voltage generation circuit 31 is provided with a common voltage generator 31a, and a common voltage compensator 31b. The common voltage generator 31a generates the common voltage, and the common voltage compensator 31b receives the common voltage outputted from the common voltage generator 31a, and outputs a compensated common voltage.
The common voltage generator 31a is connected in series between a reference voltage VDD and a ground terminal, wherein the common voltage generator 31a is formed of resistances R1, R2 and R3, including a variable resistor to divide the reference voltage. The common voltage compensator 31b is comprised of a differential amplifier A, a capacitor C1 and a resistance R4 connected in series to an inverting terminal (−) of the differential amplifier A. The common voltage which is output from the common voltage generator 31a is input to an non-inverting terminal (+) of the differential amplifier A. A resistance R6 is connected ins series with an output terminal of the differential amplifier A and a resistance R5 connects the output terminal with the inverting terminal (−).
The gate signal output from a gate signal generator (not shown) is applied to the gate line G, the gate signal comprising a gate high signal Vgh and a gate low signal Vgl. The gate low signal Vgl of the D.C. level is inputted to the inverting terminal (−) of the differential amplifier A through the capacitor C1 and the resistance R4. At this time, the gate low signal Vgl inputted to the inverting terminal (−) acts as a sensing signal to sense the distortion of the common voltage, when the common voltage is applied to the common electrode C.
That is, the gate signal applied to the gate line G is distorted by the waveform of the gray level voltage of the data line D due to the coupling phenomenon generated by the parasitic capacitance Cgd formed between the data line D and the gate line G. The gate low signal Vgl is changed to the distortion signal of the A.C. level having the repetitive rising ripple and falling ripple by the waveform of the gray level voltage.
An operation of the common voltage generation circuit 31 according to the related art will be described as follows. The reference voltage is divided by controlling the variable resistor, thereby outputting the common voltage. The gate low signal Vgl outputted from the gate signal generator is inputted to the inverting terminal (−) of the differential amplifier A through the capacitor C1 and the resistance R4. The gate low signal Vgl is not distorted, so that the gate low signal Vgl is maintained at the D.C. level. As a result, the gate low signal Vgl is not transmitted through the capacitor C1 connected in series to the inverting terminal (−) of the differential amplifier A. Thus, the differential amplifier A applies the common voltage inputted from the common voltage generator 31a to the common electrode C.
When the gate low signal Vgl has an A.C. level due to the distortion of the gate low signal Vgl generated by the coupling phenomenon, the gate low signal Vgl passes through the capacitor C1 and the resistance R4 connected to the inverting terminal (−) of the differential amplifier A. The differential amplifier A amplifies the difference between the common voltage of the D.C. level inputted to the non-inverting terminal (+) and the gate low signal inputted to the inverting terminal (−). As a result, as shown in FIG. 5, the gate low signal Vgl and the compensated common voltage having a phase difference of 180° are outputted through the output terminal. The amplification of the compensated common voltage is determined by the value of the resistance R4 connected to the inverting terminal (−) of the differential amplifier A and the resistance R5 connected between the inverting terminal (−) and the output terminal. The compensated common voltage is applied to the common electrode C. The A.C. component (ripple) of the compensated common voltage is offset by the coupled gray level voltage signal having the opposite phase to the compensated common voltage. As a result, the compensated common voltage has a constant D.C. level.
However, the related art common voltage generation circuit has the following disadvantages. The gate low signal is used to sense whether the common voltage is distorted by the coupling phenomenon or not. The gate low signal has noise since the gate low signal is provided to generate the gate signal. Accordingly, the gate low signal has the ripple generated by noise as well as the ripple generated by the coupling phenomenon. If the noise is amplified in the differential amplifier, the common voltage inputted to the differential amplifier is distorted in an undesired direction by the noise.